With the tendency towards miniaturization and multifunctional development of electronic devices, semiconductor devices are forced to be highly integrated. In response to this demand, the so-called Multi-chip Package has been proposed, which involves the integration and stacking of a plurality of chips, as well as the use for limited space.
FIGS. 1 and 2 illustrate a schematic view of a conventional stacked structure of chips, respectively. FIG. 1 shows that each of chip layer (for example 90a) includes a substrate 901, a dielectric layer 902 formed on the substrate 901, an internal circuit 912 surrounded by the dielectric layer 902, and a metallic layer 911 formed on the dielectric layer 902 connected to the internal circuit 912 through a through hole via 903. When the conventional through silicon via (TSV) 93a and 93b are utilized for two chip layers 90a and 90b in stacking process, the metallic layer 911 is coupled to the internal circuit 912 and engaged to solder bumps 92 on the back side of top chip 90a. 
On the other hand, as shown in FIG. 2, if the upper and lower chip layers 95a, 95b need to be distinguished or selected respectively, it usually add a second metallic layer 96 to achieve the purpose. The disadvantage is the need of at least two metal layers such that manufacturing costs will be increased.
Currently, many improved stacked structures are proposed, for example, U.S. Pat. No. 7,816,776 described therein, which characterized in that two adjacent chips layers have a symmetrical connection bumps and through hole via so that a parallel path and a serial path can be formed, and with operation of internal circuit to differentiate each chip layer of chips layers.